Non-volatile memory, non-volatile memory cell and operation thereof

ABSTRACT

A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a non-volatile memory device. Moreparticularly, the present invention relates to a non-volatile memorywith non-volatile memory cell having asymmetrical doped structure andmethod of operating the memory cell.

2. Description of the Related Art

Electrically erasable programmable read only memory (EEPROM) is a typeof non-volatile memory that allows multiple data writing, reading anderasing operations. The stored data will be retained even after power tothe device is removed. With these advantages, EEPROM become one of themost widely adopted non-volatile memories for personal computer andelectronic equipment.

A typical EEPROM has a floating gate and a control gate fabricated usingdoped polysilicon. To program data into the memory, electrons injectedinto the floating gate are distributed evenly within the polysiliconfloating gate layer. Obviously, if there are some defects in thetunneling oxide layer underneath the polysilicon floating gate layer,the device may leak and lead to a drop in reliability.

At present, a type of flash memory cell that programs through hot-holeinjection nitride electron storage (PHINES) has been developed as shownin FIG. 1.

FIG. 1 is a schematic cross-sectional view of a conventional programmingthrough hot-hole injection nitride electron storage (PHINES) type flashmemory cell. As shown in FIG. 1, the flash memory cell 10 typicallycomprises a substrate 100, a control gate 120 over the substrate 100, asource 130 a and a drain 130 b within the substrate 100 and anoxide/nitride/oxide (ONO) layer 110 between the control gate 120 and thesubstrate 100. The oxide/nitride/oxide (ONO) layer 110 comprises twosilicon oxide layers 112 and 116 and a silicon nitride layer 114sandwiched between them. In general, the silicon nitride layer 114serves as a charge-trapping layer therein.

The PHINES type flash memory cell in FIG. 1 utilizes band-to-bandtunneling hot-hole (BTBTHH) to program data and utilizes the uniformFowler-Nordheim (FN) channel to erase data.

Although the advantages of PHINES type flash memory cell includes lowpower consumption, a low leakage current and a simplified manufacturingmethod, some unavoidable defects are still present. For example, aPHINES type flash memory cell is designed to store a bit of data nearthe drain region and another bit of data near the source region.However, if the drain region has already stored up a single data bit,the second bit effect is produced when a reverse reading operation iscarried out. The second bit effect often leads to a drop in thethreshold voltage (Vt) in reverse reading and hence requires a higherbias voltage for reading. Yet, with a high read-out bias voltage,read-out interference will be intensified. Furthermore, the PHINES typeflash memory cell has a relatively slow programming speed. In addition,a typical PHINES flash memory cell needs to incorporate three sets ofbit line selection transistors (BLT) for programming. Hence, theoverhead area for accommodating the bit line selection transistors islarge and the actual packing density of the memory cell array isreduced.

SUMMARY OF THE INVENTION

Accordingly, one aspect of the present invention is to provide anon-volatile memory cell capable of increasing the operating speed andpreventing neighboring cell disturb issue.

Further aspect of the present invention is to provide a non-volatilememory capable of increasing the operating speed, avoiding undesirablesecond bit effect and reducing area occupation of bit line selectiontransistors.

Another aspect of the present invention is to provide a method ofoperating a non-volatile memory capable of simplifying operation andreducing the number of bit line selection transistors used in thenon-volatile memory.

To achieve these and other advantages, as embodied and broadly describedherein, the invention provides a non-volatile memory cell. Thenon-volatile memory cell comprises a substrate, a charge-trapping layerover the substrate, a control gate over the charge-trapping layer, afirst dielectric layer between the substrate and the charge-trappinglayer, a second dielectric layer between the control gate and thecharge-trapping layer, a first conductive state of source and drain, afirst conductive state of lightly doped region and a second conductivestate of pocket-doped region. The source and the drain are disposed inthe substrate on each side of the charge-trapping layer. The firstconductive state lightly doped region is disposed on the substratesurface between the source and the charge-trapping layer. The secondconductive type pocket-doped region is disposed in the substrate betweenthe drain and the charge-trapping layer.

According to a first embodiment of the non-volatile memory cell in thepresent invention, the charge-trapping layer can be a layer fabricatedfrom silicon nitride or a suitable material.

According to a first embodiment of the non-volatile memory cell in thepresent invention, the first conductive state is N-type and the secondconductive state is P-type.

The present invention also provides a non-volatile memory comprising asubstrate, a plurality of first conductive state of buried bit lineswithin the substrate, a plurality of word lines over the substrate andcrossing over the buried bit lines, a charge-trapping layer between theword lines and the substrate that between the buried bit lines, a firstdielectric layer between the charge-trapping layer and the substrate, asecond dielectric layer between the word lines and the charge-trappinglayer, a first conductive state of lightly doped region and a secondconductive type pocket-doped region. The lightly doped region isdisposed on the substrate surface on one side of the buried bit lines.The pocket-doped region is disposed in the substrate on another side ofthe buried bit lines.

According to a second embodiment of the non-volatile memory in thepresent invention, the charge-trapping layer can be a layer fabricatedfrom silicon nitride or a suitable material.

According to a second embodiment of the non-volatile memory in thepresent invention, the first conductive state is N-type and the secondconductive state is P-type.

According to a second embodiment of the non-volatile memory in thepresent invention, the non-volatile memory further comprises two bitline selection transistors connected to the buried bit lines.

The present invention also provides a method of operating a non-volatilememory cell. The non-volatile memory cell comprises a substrate; a firstconductive state of first drain, a second drain and a source in thesubstrate; a word line over the substrate and crossing over the first,the second drain and the source; a charge-trapping layer between theword lines and the substrate that between the first, the second drainsand the source; a first dielectric layer between the charge-trappinglayer and the substrate; a second dielectric layer between the wordlines and the charge-trapping layer; a first conductive state of lightlydoped region in the substrate surface on one side of each drain andsource; and, a second conductive state of pocket-doped region on theother side of each drain and source. To initiate a programmingoperation, a first bias voltage is applied to the word line and a secondbias voltage is applied to the source, the first drain is connected to aground and the second drain is set to a floating state. The first biasvoltage is lower than the second bias voltage.

The method of operating a non-volatile memory cell according to thepresent invention further includes an erasing operation. To initiate anerasing operation, a bias voltage for triggering a channel F-N erasingoperation is applied to the word line, the first drain and the sourceare connected to a ground and the second drain is set to a floatingstate.

The method of operating a non-volatile memory cell according to thepresent invention further includes a reading operation. To initiate areading operation, a third bias voltage is applied to the word line, avoltage lower than the third bias voltage is applied to the first drain,the source is connected to a ground and the second drain is set to afloating state.

In the present invention, an implant structure having an asymmetricalconfiguration and different doped states is applied to a non-volatilememory cell that programs by hot-hole injection nitride electron storage(PHINES). Therefore, programming speed can be increased throughincreasing the implant dosage while forming the pocket-doped region, andthe reading capacity will not be affected. Furthermore, because thelightly doped region in the present invention deploys a low read-outbias voltage, a channel with a higher threshold voltage (Vt) can be usedfor reading, and the neighboring cell disturb issue is furtherprevented. In addition, the lightly doped region is able to lower theproduction of channel hot electrons (CHE) and hence avoids the read-outdistribution problem during a reverse reading operation. Moreover, thepresent invention also disposes of the need to form isolation linesbetween memory cells so that the programming system and circuits arevery much simplified. Additionally, only a single group of bit linesneeds to be controlled during a programming operation in thenon-volatile memory cell of the present invention so that the area foraccommodating the bit line selection transistors can be reduced.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a schematic cross-sectional view of a conventional programmingthrough hot-hole injection nitride electron storage (PHINES) type flashmemory cell.

FIG. 2 is a schematic cross-sectional view of a non-volatile memory cellaccording to a first embodiment of the present invention.

FIG. 3A is an equivalent circuit diagram of a non-volatile memoryaccording a second embodiment of the present invention.

FIG. 3B is a schematic cross-sectional view of the labeled section B ofthe non-volatile memory in FIG. 3A.

FIG. 3C is another schematic cross-sectional view of the labeled sectionB of the non-volatile memory in FIG. 3A.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

According to the present invention, a non-volatile memory, anon-volatile memory cell and a method of operating the non-volatilememory cell having a programming by hot-hole injection nitride electronstorage (PHINES) is provided.

FIG. 2 is a schematic cross-sectional view of a non-volatile memory cellaccording to a first embodiment of the present invention. As shown inFIG. 2, the non-volatile memory cell 20 of the present inventioncomprises a substrate 200, a charge-trapping layer 214 on the substrate200, a control gate 220 over the charge-trapping layer 214, a firstdielectric layer 212 between the substrate 200 and the charge-trappinglayer 214, a second dielectric layer 216 between the control gate 220and the charge-trapping layer 214, a first conductive state of source230 a and drain 230 b, a first conductive state of lightly doped region202 and a second conductive state of pocket-doped region 204. In thepresent invention, the first conductive state is N-type and the secondconductive state is P-type, for example. The source 230 a and the drain230 b are disposed in the substrate 200 on each side of thecharge-trapping layer 214. A channel region (not shown) is formed in thesubstrate 200 between the source 230 a and the drain 230 b. The firstconductive state of lightly doped region 202 is disposed close to thetop surface of the substrate 200 between the source 230 a and thecharge-trapping layer 214 and the second conductive state ofpocket-doped region 204 is disposed in the substrate between the drain230 b and the charge-trapping layer 214. The substrate 200 can befabricated from a conventional semiconductor material such as silicon.The charge-trapping layer 214 can be fabricated using silicon nitride orother suitable material. Both the first dielectric layer 212 and thesecond dielectric layer 216 can be fabricated using a single type ofmaterial such as silicon oxide or other suitable material or they arefabricated from different types of materials.

The electron and hole distribution profile in the charge-trapping layer214 when the memory cell 20 is being programmed is shown in FIG. 2. Thenon-volatile memory 20 in FIG. 2 uses a band-to-band tunneling hot-holemethod for a programming operation and a uniform F-N channel for anerasing operation. In addition, the memory cell 20 of the presentembodiment can also be used in a multi-bit-per-cell system. In otherwords, a multiple level threshold voltage can be established on theright side of the non-volatile memory 20 through the band-to-bandtunneling hot-hole to obtain more memory states. For example, a 4-levelthreshold voltage (Vt) design can be used to produce a memory statehaving 2-bit per memory cell storage capacity. However, the left side orright side is a type of usage that refers to the disposition relative toa memory cell. This type of language usage can be changed according tothe location of the lightly doped region 202 and the pocket-doped region204 without any effect on the function of the memory cell.

When the memory cell 20 of the present invention operates according tothe PHINES method of operation, the drain 230 b having a pocket-dopedregion 204 can enhance the programming efficiency of band-to-bandtunneling hot-hole so that the programming speed is increased.Furthermore, the source 230 a having a lightly doped region 202 is ableto restrict the production of the band-to-band tunneling hot holes.Therefore, there is no need to settle for a conventional bitconstraining method in the non-volatile memory cell of the presentinvention.

In addition, the non-volatile memory cell of the present embodiment hasan asymmetrically doped structure. Hence, the implant dosage of thepocket-doped region 204 can be increased to prevent a punch through ofthe lightly doped region 202 and increase the programming speed of thememory cell at the same time.

FIG. 3A is an equivalent circuit diagram of a non-volatile memoryaccording a second embodiment of the present invention. FIG. 3B is aschematic cross-sectional view of the labeled section B of thenon-volatile memory in FIG. 3A. FIG. 3C is another schematiccross-sectional view of the labeled section B of the non-volatile memoryin FIG. 3A. As shown in FIGS. 3A and 3B first, the non-volatile memorymainly comprises a substrate 300, a plurality of first conductive stateof buried bit lines 330 in the substrate 300, a plurality of word lines320 over the substrate 300 and crossing over the buried bit lines 330, acharge-trapping layer 314 between the word lines 320 and the substrate300 that between the buried bit lines 330, a first dielectric layer 312between the charge-trapping layer 314 and the substrate 300, a seconddielectric layer 316 between the word lines 320 and the charge-trappinglayer 314, a first conductive state of lightly doped region 302 and asecond conductive state of pocket-doped region 304. The first conductivestate is N-type and the second conductive state is P-type, for example.The lightly doped region 302 is disposed near the top surface of thesubstrate 300 on one side of the buried bit lines 330 while thepocket-doped region 304 is disposed in the substrate 300 on the otherside of the buried bit lines 330.

In addition, refer to FIGS. 3B and 3C, a dielectric layer 306 maycompletely fill the space between the charge-trapping layer 314 and eachof the word lines 320 so that they are isolated from each other as shownin FIG. 3B, or the first dielectric layer 312, the charge-trapping layer314 and the second dielectric layer 316 are extended over the entiresubstrate 300 as shown in FIG. 3C.

Moreover, in order to operate the memory, two bit line selectiontransistors 350 are incorporated for electrically connecting with theburied bit lines 330 with the word lines 320.

To initiate a programming operation of the memory cell on the left sideof BS (serving as the source of the buried bit line 330), a first biasvoltage is applied to WL (the word line 320), a second bias voltage isapplied to BS, the line BDL (serving as the first drain of the buriedbit line 330) is connected to a ground and the line BDR (serving as thesecond drain of the buried bit line 330) is set to a floating state. Thefirst bias voltage is lower than the second bias voltage. Meanwhile, thebit line on the right side of BS is constrained because of the floatingBDR line and the presence of the n-type lightly doped region 302. Itshould be noted that the left side or right side is a type of languageusage that refers to the disposition relative to a memory cell. Thistype of language usage can be changed according to the location of thelightly doped region 302 and the pocket-doped region 304 without anyeffect on the function of the memory.

To erase memory data from the memory cell, a bias voltage capable oftriggering an F-N channeling erase operation is applied to the WL line,the BDL and the BS line are connected to a ground and the BDR line isset to a floating state. As a result, electrons are trapped inside thecharge-trapping layer 324.

To read data from the memory cell, a reverse reading method can beexecuted. In the reverse reading operation, a third bias voltage isapplied to the WL line, a voltage lower than the third bias voltage isapplied to the BDL line, the BS line is connected to a ground and theBDR line is set to a floating state.

In table 1 below, the values of the bias voltage for operating thenon-volatile memory are shown. According to table 1, only two bit lineselection transistors 350 are required to control a group of word linesWL and a group of bit lines BS in programming the memory of the presentembodiment. In addition, a bias voltage smaller than 1.6V applied to theBDL line can be used to carry out a reading operation. TABLE 1 (unit: V)BDL BS BDR WL FN-erase 0 0 Floating −20 HH-program 0 5 Floating −5 Read<1.6 0 Floating 5

In summary, major aspects of the present invention are as follows.

1. An implant structure having an asymmetrical configuration anddifferent doped states is applied to a non-volatile memory cell thatprograms by hot-hole injection nitride electron storage (PHINES).Therefore, programming speed can be increased through increasing theimplant dosage while forming the pocket-doped region, and the readingcapacity will not be affected. Moreover, the lightly doped regionutilized in the present invention can prevent the neighboring celldisturb issue caused by programming.

2. Because the lightly doped region in the present invention deploys alow read-out bias voltage, a channel with a higher threshold voltage(Vt) can be used for reading. In addition, the lightly doped region isable to lower the production of channel hot electrons (CHE) and henceavoids the read-out distribution problem during a reverse readingoperation.

3. The present invention also disposes of the need to form isolationlines between memory cells so that the programming system and circuitsare very much simplified.

4. Only a single group of bit lines needs to be controlled during aprogramming operation in the non-volatile memory cell of the presentinvention so that the area for accommodating the bit line selectiontransistors can be reduced.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A non-volatile memory cell, comprising: a substrate; acharge-trapping layer disposed over the substrate; a control gatedisposed over the charge-trapping layer; a first dielectric layerdisposed between substrate and the charge-trapping layer; a seconddielectric layer disposed between the control gate and thecharge-trapping layer; a first conductive state of a source and a firstconductive state of a drain disposed in the substrate on each side ofthe charge-trapping layer; a first conductive state of a lightly dopedregion disposed in the substrate between the source and thecharge-trapping layer; and a second conductive state of a pocket-dopedregion disposed in the substrate between the drain and thecharge-trapping layer.
 2. The non-volatile memory cell of claim 1,wherein the charge-trapping layer comprises a silicon nitride layer. 3.The non-volatile memory cell of claim 1, wherein the first conductivestate is N-type.
 4. The non-volatile memory cell of claim 1, wherein thesecond conductive state is P-type.
 5. The non-volatile memory cell ofclaim 1, wherein the memory cell also comprises a channel region withinthe substrate between the source and the drain.
 6. A non-volatilememory, comprising: a substrate; a plurality of first conductive stateof a buried bit lines disposed in the substrate; a plurality of wordlines over the substrate and crossing over the buried bit lines; acharge-trapping layer disposed between the word lines and the substratethat between the buried bit lines; a first dielectric layer between thecharge-trapping layer and the substrate; a second dielectric layerbetween the word lines and the charge-trapping layer; a first conductivestate of a lightly doped region disposed close to the top of thesubstrate on one side of the buried bit lines; and a second conductivestate of a pocket-doped region disposed in the substrate on another sideof the buried bit line.
 7. The non-volatile memory of claim 6, whereinthe charge-trapping layers comprise silicon nitride layers.
 8. Thenon-volatile memory of claim 6, wherein the first conductive state isN-type.
 9. The non-volatile memory of claim 6, wherein the secondconductive state is P-type.
 10. The non-volatile memory of claim 6,wherein the memory further comprises a channel region disposed in thesubstrate between the buried bit lines.
 11. The non-volatile memory ofclaim 6, wherein the memory further comprises two bit line selectiontransistors electrically connected to the buried bit lines.
 12. Thenon-volatile memory of claim 6, wherein the first dielectric layer, thecharge-trapping layer and the second dielectric layer are extended overthe entire substrate.
 13. A method of operating a non-volatile memorycell having a first conductive state of a first drain, a second drainand a source in a substrate, a word line crossing over the first, thesecond drain and the source, a charge-trapping layer between the wordlines and the substrate that between the first, the second drains andthe source, a first dielectric layer between the charge-trapping layerand the substrate, a second dielectric layer between the word lines andthe charge-trapping layer, a first conductive state of a lightly dopedregion close to the top surface of the substrate on one side of eachfirst, the second drain and the source, and a second conductive state ofa pocket-doped region on another side of each first, the second drainand the source, the operating method comprising the steps of: performinga programming operation by applying a first bias voltage to the wordlines, applying a second bias voltage to the source, connecting thefirst drain to a ground and setting the second drain to a floatingstate, wherein the first bias voltage is lower than the second biasvoltage.
 14. The operating method of claim 13, wherein the methodfurther comprises: performing an erasing operation by applying a biasvoltage to the word lines for executing a F-N channeling eraseoperation, connecting the first drain and the source to a ground andsetting the second drain to a floating state.
 15. The operating methodof claim 13, wherein the method further comprises: performing a readingoperation by applying a third bias voltage to the word lines, applying avoltage lower than the third bias voltage to the first drain, connectingthe source to a ground and setting the second drain to a floating state.